Project Description (pdf)

In the Objective ICT-2009.3.4 "Embedded Systems Design", a strong focus is placed on the development of novel (generic) design methodologies that can be applied to several application areas. In the ERA project, we describe a platform that can adapt itself through coarse-grain reconfigurable hardware to tailor the hardware itself for changing environments and needs of the applications running on the platform, for different application markets and platform usage. We identified the following main objectives:

  • to define and develop a dynamically reconfigurable integrated platform composed by the following components: a parameterized VLIW processor, a reconfigurable NoC, and a memory subsystem - taking into account power consumption as design parameter.

  • to provide the support for flexible and fast reconfiguration of the platform by using direct hardware support as well as partial FPGA reconfiguration.

  • to provide the needed hardware monitoring and low-level OS support to efficiently control the hardware reconfiguration.

  • to benchmark and analyze a set of existing applications in the area of mobile processing to extract a set of off-line and on-line measurable parameters.

  • to build a supervisor which will be able to monitor the parameters and react to online application changes to appropriately reconfigure the hardware.

The envisioned adaptive ERA platform employs a structured design approach that allows integration of varying computing elements, networking elements, and memory elements. For computing elements, we will utilize a mixture of commercially available off-the-shelf processor cores, industry-owned IP cores, and application-specific/dedicated cores, and we will dynamically adapt their composition, organization, and even instruction-set architectures to provide the best possible performance/power trade-offs. Similarly, the choice of the most-suited network elements and topology and the adaptation of the hierarchy and organization of the memory elements can be determined at design-time or at run-time. Furthermore, the envisioned adaptive platform must be supported by and/or made visible to the application(s), run-time system, operating system, and compiler exploiting the synchronicities between software and hardware. We strongly believe that having the complete freedom to flexibly tune the hardware elements will allow for a much higher level of efficiency (e.g., riding the trade-off curve between performance and power). Finally, an additional goal of the adaptive platform is to serve as a quick prototyping platform in embedded systems de-sign.